ATxmega128D4 Atmel Corporation, ATxmega128D4 Datasheet - Page 47
ATxmega128D4
Manufacturer Part Number
ATxmega128D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128D4
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega128D4-CU
Manufacturer:
MICROCH
Quantity:
20 000
Company:
Part Number:
ATxmega128D4-MH
Manufacturer:
SIRENZA
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7 600
Company:
Part Number:
ATxmega128D4-U
Manufacturer:
ATMEL
Quantity:
1
Part Number:
ATxmega128D4-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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5.5
8210B–AVR–04/10
Event Timing
Figure 5-3.
Having four multiplexers means that it is possible to route up to four events at the same time. It
is also possible to route one event through several multiplexers.
Not all XMEGA parts contain all peripherals. This only means that peripheral is not available for
generating or using events. The network configuration itself is compatible between all devices.
An event normally lasts for one peripheral clock cycle, but some event sources, such as low
level on an I/O pin, will generate events continuously. Details on this are described in the
(8)
(8)
(8)
(8)
(8)
Event Routing Network
(PORTC)
(PORTD)
(PORTE)
(PORTF)
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
ADCA
TCC0
TCC1
TCD0
TCE0
TCF0
RTC
AC0
AC1
(8)
(8)
(8)
(8)
(8)
(4)
(8)
(8)
(8)
(8)
(8)
(8)
Event Channel 3
Event Channel 2
Event Channel 1
Event Channel 0
(16)
(48)
(7)
XMEGA D
CH0CTRL[7:0]
CH1CTRL[7:0]
CH2CTRL[7:0]
CH3CTRL[7:0]
CH0MUX[7:0]
CH1MUX[7:0]
CH2MUX[7:0]
CH3MUX[7:0]
47
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