ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 251
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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21.15.3
21.15.4
8077H–AVR–12/09
CTRLA – USART Control Register A
CTRLB - USART Control Register B
• Bit 0 - RXB8: Receive Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. When used, this bit must be read before reading the low bits from DATA.
This bit unused in Master SPI mode of operation.
• Bit 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:4 - RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the Receive Complete Interrupt and select the interrupt level as described in
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
enabled interrupt will be triggered when the RXCIF in the STATUS register is set.
• Bit 3:2 - TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the Transmit Complete Interrupt and select the interrupt level as described in
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
enabled interrupt will be triggered when the TXCIF in the STATUS register is set.
• Bit 1:0 - DREINTLVL[1:0]: USART Data Register Empty Interrupt Level
These bits enable the Data Register Empty Interrupt and select the interrupt level as described
in
enabled interrupt will be triggered when the DREIF in the STATUS register is set.
• Bit 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - RXEN: Receiver Enable
Setting this bit enables the USART Receiver. The Receiver will override normal port operation
for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the
FERR, BUFOVF, and PERR flags.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
R
R
7
0
7
0
-
-
R
R
6
0
6
0
-
-
R/W
R
5
RXCINTLVL[1:0]
0
5
0
-
RXEN
R/W
R/W
4
0
4
0
TXEN
R/W
R/W
3
TXCINTLVL[1:0]
0
3
0
CLK2X
R/W
R/W
2
0
2
0
MPCM
R/W
R/W
1
DREINTLVL[1:0]
0
1
0
XMEGA A
TXB8
R/W
R/W
0
0
0
0
123. The
123. The
123. The
CTRLA
CTRLB
251
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