ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 340
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
953
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28.4.2
28.4.3
28.4.4
28.4.5
28.4.6
8077H–AVR–12/09
IDCODE; 0x3
SAMPLE/PRELOAD; 0x2
BYPASS; 0xf
CLAMP; 0x4
HIGHZ; 0x5
The active states are:
IDEOCE is mandatory and the instruction for selecting the 32 bit ID-Register as Data Register.
The ID-Register consists of a version number, a device number and the manufacturer code cho-
sen by JEDEC. This is the default instruction after power-up.
The active states are:
SAMPLE/RELOAD mandatory and the instruction for pre-loading the output latches and taking a
snapshot of the input/output pins without affecting system operation. However, the output
latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
Note that since each of the SAMPLE and PRELOAD instructions implements the functionality of
the other, they share a common binary value, and can be treated as one single merged
instruction.
The active states are:
BYPASS is mandatory and the instruction for selecting the Bypass Register for Data Register.
The active states are:
CLAMP is optional and the instruction for allowing the state of the input/output pins to be deter-
mined from the preloaded output latches. The Bypass register is selected as Data Register.
The active states are:
HIGHZ is optional and the instruction for putting all outputs in an inactive drive state (e.g. high
impedance). The Bypass register is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: Data in the Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
• Capture-DR: Data in the IDCODE Register is sampled into the Device Identification register.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
• Capture-DR: Loads a logic "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
• Capture-DR: Loads a logical "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
the output latches are not connected to the pins.
XMEGA A
340
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