ATxmega64D4 Atmel Corporation, ATxmega64D4 Datasheet - Page 173
ATxmega64D4
Manufacturer Part Number
ATxmega64D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64D4
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega64D4-AU
Manufacturer:
AT
Quantity:
20 000
Company:
Part Number:
ATxmega64D4-H
Manufacturer:
ATMEL
Quantity:
5
Company:
Part Number:
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Manufacturer:
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86
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8210B–AVR–04/10
Figure 16-5. Master Write Transaction
Given that the slave acknowledges the address, the master can start transmitting data (DATA)
and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the
master terminates the transaction by issuing a STOP condition (P) directly after the address
packet. There are no limitations to the number of data packets that can be transferred. If the
slave signal a NACK to the data, the master must assume that the slave cannot receive any
more data and terminate the transaction.
Figure 16-6
ing a START condition followed by an address packet with direction bit set to one (ADRESS+R).
The addressed slave must acknowledge the address for the master to be allowed to continue
the transaction.
Figure 16-6. Master Read Transaction
Given that the slave acknowledges the address, the master can start receiving data from the
slave. There are no limitations to the number of data packets that can be transferred. The slave
transmits the data while the master signals ACK or NACK after each data byte. The master ter-
minates the transfer with a NACK before issuing a STOP condition.
Figure 16-7
and write transactions separated by a Repeated START conditions (Sr).
Figure 16-7. Combined Transaction
S
S
S
ADDRESS
Address Packet #1
illustrates the Master Read transaction. The master initiates the transaction by issu-
illustrates a combined transaction. A combined transaction consists of several read
ADDRESS
ADDRESS
Address Packet
Address Packet
R/W
A
Direction
W
R
N Data Packets
DATA
A
A
A/A
Transaction
Transaction
DATA
DATA
Transaction
Data Packet
Data Packet
Sr
ADDRESS
Address Packet #2
N data packets
N data packets
A
A
R/W
A
DATA
DATA
Direction
M Data Packets
DATA
XMEGA D
A/A
A
A/A P
P
P
173
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