SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 110
SAM3N1A
Manufacturer Part Number
SAM3N1A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1A
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.13.3
10.13.3.1
10.13.3.2
10.13.3.3
10.13.3.4
110
SAM3N
ASR, LSL, LSR, ROR, and RRX
Syntax
Operation
Restrictions
Condition flags
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
where:
op
S
result of the operation, see
Rd
Rm
Rs
significant byte is used and can be in the range 0 to 255.
n
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of
places specified by constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains
unchanged. For details on what result is generated by the different instructions, see
ations” on page
Do not use SP and do not use PC.
If S is specified:
• these instructions update the N and Z flags according to the result
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
ASR
LSL
LSR
ROR
ASR
LSL
LSR
ROR
is one of:
Arithmetic Shift Right.
Logical Shift Left.
Logical Shift Right.
Rotate Right.
is an optional suffix. If S is specified, the condition code flags are updated on the
is the destination register.
is the register holding the value to be shifted.
is the register holding the shift length to apply to the value in Rm. Only the least
is the shift length. The range of shift length depends on the instruction:
shift length from 1 to 32
shift length from 0 to 31
shift length from 1 to 32
shift length from 1 to 31.
81.
“Conditional execution” on page
84.
11011A–ATARM–04-Oct-10
“Shift Oper-
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