SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 58
SAM3N1A
Manufacturer Part Number
SAM3N1A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1A
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.5.4
10.5.4.1
10.5.4.2
10.5.4.3
58
SAM3N
Software ordering of memory accesses
DMB
DSB
ISB
Table 10-5.
1.
2.
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
“Memory system ordering of memory accesses” on page 56
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering. The
processor provides the following memory barrier instructions:
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See
Use memory barrier instructions in, for example:
Address range
0xA0000000-
0xBFFFFFFF
0xC0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
• the processor can reorder some memory accesses to improve efficiency, providing this does
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
• Vector table. If the program changes an entry in the vector table, and then enables the
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
not affect the behavior of the instruction sequence.
corresponding exception, use a DMB instruction between the operations. This ensures that if
the exception is taken immediately after being enabled the processor uses the new exception
vector.
immediately after the code modification in the program. This ensures subsequent instruction
execution uses the updated program.
See
The Peripheral and Vendor-specific device regions have no additional access constraints.
“Memory regions, types and attributes” on page 55
Memory region share ability policies (Continued)
Memory region
External device
Private Peripheral
Bus
Vendor-specific
device
(2)
Memory type
Device
Strongly-
ordered
Device
“DMB” on page
(1)
(1)
(1)
for more information.
“DSB” on page
“ISB” on page
describes the cases where the
Shareability
Shareable
Non-
shareable
Shareable
-
140.
(1)
(1)
(1)
142.
11011A–ATARM–04-Oct-10
141.
-
-
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