SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 105

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.13.1
10.13.1.1
10.13.1.2
10.13.1.3
6500C–ATARM–8-Feb-11
ADD, ADC, SUB, SBC, and RSB
Syntax
Operation
Restrictions
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
where:
op
S
result of the operation, see
cond
Rd
Rn
Operand2
imm12
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is
clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see
page
See also
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the
SUB syntax that uses the imm12 operand.
In these instructions:
• Operand2 must not be SP and must not be PC
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
107.
ADD
ADC
SUB
SBC
RSB
“ADR” on page
is one of:
Add.
Add with Carry.
Subtract.
Subtract with Carry.
Reverse Subtract.
is an optional suffix. If S is specified, the condition code flags are updated on the
is an optional condition code, see
is the destination register. If Rd is omitted, the destination register is Rn.
is the register holding the first operand.
is a flexible second operand.
See
is any value in the range 0-4095.
“Flexible second operand” on page 80
88.
“Conditional execution” on page
“Conditional execution” on page
; ADD and SUB only
for details of the options.
84.
“Multiword arithmetic examples” on
84.
SAM3S
105