SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 1075

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

41.11.5.1
Table 41-46. SSC Timings
Notes:
6500C–ATARM–8-Feb-11
Symbol
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1)
(1)
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
3. 1.8V domain: V
4. 3.3V domain: V
7(Receive Start Selection), two Periods of the MCK must be added to timings.
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization.
41-25
Parameter
TK edge to TF/TD (TK output, TF output)
TK edge to TF/TD (TK input, TF output)
TF setup time before TK edge (TK output)
TF hold time after TK edge (TK output)
TK edge to TF/TD (TK output, TF input)
TF setup time before TK edge (TK input)
TF hold time after TK edge (TK input)
TK edge to TF/TD (TK input, TF input)
RF/RD setup time before RK edge (RK input)
RF/RD hold time after RK edge (RK input)
RK edge to RF (RK input)
RF/RD setup time before RK edge (RK output)
RF/RD hold time after RK edge (RK output)
RK edge to RF (RK output)
SSC Timings
illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
VDDIO
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 25 pF.
from 3.0V to 3.6V, maximum external capacitor = 25 pF.
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
Transmitter
Condition
Receiver
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
6.5 (+3*t
1.5(+2*t
1.4(+2*t
6(+3*t
16.5- t
t
19 - t
19- t
16- t
CPMCK
t
t
t
CPMCK
CPMCK
CPMCK
6.2
5.5
1.2
1.4
13.5
14.5
0.25
15
CPMCK
Min
6
1.5
1.4
0.8
1.2
1.7
CPMCK
CPMCK
CPMCK
CPMCK
CPMCK
1
0
(2)
CPMCK
(2)
CPMCK
(2)
(2)
(2)
(2)
- 5.7
- 6
- 5
- 5
)
(1)(2)
)
)
)
(1)(2)
(1)(2)
(1)(2)
30.5(+2*t
20 (+3*t
30(+2*t
18(+3*t
16.5
Max
30.3
30.5
21
18
19
29
30
CPMCK
CPMCK
CPMCK
CPMCK
(2)
(2)
(2)
(2)
(2)
(2)
)
)
)
SAM3S
(1)(2)
(1)(2)
)
(1)(2)
(1)(2)
Figure
Units
1075
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns