SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 1098

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

44.2
44.2.1
44.2.1.1
44.2.1.2
44.2.1.3
44.2.2
44.2.2.1
44.2.2.2
1098
Errata Revision A Parts
SAM3S
Flash Memory
Analog-to-Digital Converter (ADC)
FLASH: Flash Reading in 64-bit mode
FLASH: Flash issue running at frequency lower than 5 MHz
FLASH: Flash Programming
ADC: Comparison Window, High Threshold Value
ADC: End of Conversion (EOC) Flag
Revision A parts Chip IDs are as follows:
Higher power consumption than expected can be seen when reading Flash in 64-bit mode.
Use 128-bit mode instead.
When the system clock (MCK) is lower than 5 MHz with 2 Wait States (WS) programmed in the
EEFC_FMR, the Cortex fetches erroneous instructions.
Do not use 2 WS when running at a frequency lower than 5 MHz.
When writing data into the Flash memory plane (either through the EEFC, using the IAP function
or FFPI), the data may not be correctly written (i.e the data written is not the one expected).
Set the number of Wait States (WS) at 6 (FWS = 6) during the programming.
High threshold bits[27:16] of the ADC Compare Window Register (ADC_CWR) are not function-
ally read/write and return 0 when ADC_CWR register is read. However, the high threshold value
is correctly registered and behaves accordingly.
Ignore the read value of ADC_CWR high threshold bits [27:16].
Performing a software reset (SWRST bit in ADC_CR) does not reset the EOCx flags of the ADC
Interrupt Status Register.
Reading the ADC_CDRx channels clears the corresponding EOCx flag.
• SAM3S4C (Rev A)
• SAM3S2C (Rev A)
• SAM3S1C (Rev A)
• SAM3S4B (Rev A)
• SAM3S2B (Rev A)
• SAM3S1B (Rev A)
• SAM3S4A (Rev A)
• SAM3S2A (Rev A)
• SAM3S1A (Rev A)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
0x28900960
0x289A0760
0x28990560
0x28800960
0x288A0760
0x28890560
0x28A00960
0x28AA0760
0x28A90560
6500C–ATARM–8-Feb-11