SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 127

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.16.2
10.16.2.1
10.16.2.2
10.16.2.3
10.16.2.4
10.16.2.5
6500C–ATARM–8-Feb-11
SBFX
UBFX
SBFX and UBFX
Syntax
Operation
Restrictions
Condition flags
Examples
R0, R1, #20, #4
R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
Signed Bit Field Extract and Unsigned Bit Field Extract.
where:
cond
Rd
Rn
lsb
width
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the
destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the
destination register.
Do not use SP and do not use PC
These instructions do not affect the flags.
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
; extend to 32 bits and then write the result to R8
is an optional condition code, see
is the destination register.
is the source register.
is the position of the least significant bit of the bitfield.
lsb must be in the range 0 to 31.
is the width of the bitfield and must be in the range 1 to 32−lsb.
.
“Conditional execution” on page
84.
SAM3S
127