SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 135

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.17.4
10.17.4.1
10.17.4.2
10.17.4.3
10.17.4.4
6500C–ATARM–8-Feb-11
TBB and TBH
Syntax
Operation
Restrictions
Condition flags
Table Branch Byte and Table Branch Halfword.
where:
Rn
then the address of the table is the address of the byte immediately following the TBB or TBH
instruction.
Rm
LSL #1 doubles the value in Rm to form the right offset into the table.
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index
into the table. For TBB the branch offset is twice the unsigned value of the byte returned from
the table. and for TBH the branch offset is twice the unsigned value of the halfword returned
from the table. The branch occurs to the address at that offset from the address of the byte
immediately after the TBB or TBH instruction.
The restrictions are:
These instructions do not change the flags.
• Rn must not be SP
• Rm must not be SP and must not be PC
• when any of these instructions is used inside an IT block, it must be the last instruction of the
IT block.
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
is the register containing the address of the table of branch lengths. If Rn is PC,
is the index register. This contains an index into the table. For halfword tables,
SAM3S
135