SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 187

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.21.12 Hard Fault Status Register
• DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
• FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
6500C–ATARM–8-Feb-11
DEBUGEVT
31
23
15
7
FORCED
30
22
14
6
The HFSR gives information about events that activate the hard fault handler. See the register
summary in
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0. The bit assignments are:
29
21
13
5
Table 10-30 on page 164
Reserved
28
20
12
4
Reserved
Reserved
for its attributes.
27
19
11
3
Reserved
26
18
10
2
VECTTBL
25
17
9
1
SAM3S
Reserved
24
16
8
0
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