SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 207

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.23.8.2
6500C–ATARM–8-Feb-11
Updating an MPU region using multi-word writes
However, memory barrier instructions are not required if the MPU setup process starts by enter-
ing an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the PPB, which is a Strongly-Ordered memory region.
For example, if you want all of the memory access behavior to take effect immediately after the
programming sequence, use a DSB instruction and an ISB instruction. A DSB is required after
changing MPU settings, such as at the end of context switch. An ISB is required if the code that
programs the MPU region or regions is entered using a branch or call. If the programming
sequence is entered using a return from exception, or by taking an exception, then you do not
require an ISB.
You can program directly using multi-word writes, depending on how the information is divided.
Consider the following reprogramming:
Use an STM instruction to optimize this:
You can do this in two words for pre-packed information. This means that the RBAR contains the
required region number and had the VALID bit set to 1, see
ter” on page
Use an STM instruction to optimize this:
• before MPU setup if there might be outstanding memory transfers, such as buffered writes,
• after MPU setup if it includes memory transfers that must use the new MPU settings.
that might be affected by the change in MPU settings
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
STR R1, [R0, #0x0]
STR R2, [R0, #0x4]
STR R3, [R0, #0x8]
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
STM R0, {R1-R3}
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR
STR R1, [R0, #0x0]
STR R2, [R0, #0x4]
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR
STM R0, {R1-R2}
202. Use this when the data is statically packed, for example in a boot loader:
; 0xE000ED98, MPU region number register
; Region Number
; Region Base Address
; Region Attribute, Size and Enable
; 0xE000ED98, MPU region number register
; Region Number, address, attribute, size and enable
; 0xE000ED9C, MPU Region Base register
; Region base address and
; region number combined with VALID (bit 4) set to 1
; Region Attribute, Size and Enable
; 0xE000ED9C, MPU Region Base register
; Region base address, region number and VALID bit,
“MPU Region Base Address Regis-
SAM3S
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