SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 299

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.3.3.5
6500C–ATARM–8-Feb-11
GPNVM Bit
The lock sequence is:
One error can be detected in the EEFC_FSR register after a programming sequence:
It is possible to clear lock bits previously set. Then the locked region can be erased or pro-
grammed. The unlock sequence is:
One error can be detected in the EEFC_FSR register after a programming sequence:
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC).
The Get Lock Bit status sequence is:
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock
region is locked.
One error can be detected in the EEFC_FSR register after a programming sequence:
Note:
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product defi-
nition section for information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
• The Set Lock command (SLB) and a page number to be protected are written in the Flash
• When the locking completes, the FRDY bit in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• The Clear Lock command (CLB) and a page number to be unprotected are written in the
• When the unlock completes, the FRDY bit in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• The Get Lock Bit command (GLB) is written in the Flash Command Register, FARG field is
• Lock bits can be read by the software application in the EEFC_FRR register. The first word
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the
Command Register.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the interrupt line of the NVIC is activated.
effect. The result of the SLB command can be checked running a GLB (Get Lock Bit)
command.
Flash Command Register.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the interrupt line of the NVIC is activated.
effect.
meaningless.
read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as
it is meaningful. Extra reads to the EEFC_FRR register return 0.
SGPB command and the number of the GPNVM bit to be set.
Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
SAM3S
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