SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 364

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.6
23.6.1
Figure 23-2.
23.6.1.1
Figure 23-3. NAND Flash Signal Multiplexing on SMC Pins
364
Connection to External Devices
SAM3S
Data Bus Width
NAND Flash Support
Memory Connection for an 8-bit Data Bus
* in CCFG_SMCNFCS Matrix register
NCSx (activated if SMC_NFCSx=1) *
The data bus width is 8 bits.
Figure 23-2
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller. It depends on the programming
of the SMC_NFCSx field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface.
For details on this register, refer to the Bus Matrix User Interface section. Access to an external
NAND Flash device via the address space reserved to the chip select programmed.
The user can connect up to 4 NAND Flash devices with separated chip select.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCSx programmed is active. NANDOE and NANDWE are dis-
abled as soon as the transfer address fails to lie in the NCSx programmed address space.
Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO
Mode but only in peripheral mode (NWE function). If NWE function is not used for other external
memories (SRAM, LCD), it must be configured in one of the following modes.
SMC
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
NWE
NRD
A[18:0]
NCS[2]
D[7:0]
NWE
NRD
NAND Flash Logic
Write Enable
Output Enable
Memory Enable
D[7:0]
A[18:0]
NANDOE
NANDWE
NANDOE
NANDWE
6500C–ATARM–8-Feb-11