SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 427

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6
25.6.1
6500C–ATARM–8-Feb-11
Divider and PLL Block
Divider and Phase Lock Loop Programming
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main
Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can
be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during
16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20
MHz Crystal or Ceramic Resonator-based oscillator can be determined.
The device features two Divider/PLL Blocks that permit a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device and host ports regard-
less of the frequency of the main clock.
Figure 25-4
Figure 25-4. Dividers and PLL Blocks Diagram
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL (PLLA, PLLB) allows multiplication of the divider’s outputs. The PLL clock signal has a
frequency that depends on the respective source signal frequency and on the parameters DIV
(DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is
• when the Main Clock Oscillator selection is modified
MAINCK
shows the block diagram of the dividers and PLL blocks.
SLCK
Divider B
Divider A
DIVB
DIVA
MULB
MULA
PLLACOUNT
PLLBCOUNT
PLLADIV2
PLLBDIV2
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
LOCKB
LOCKA
SAM3S
PLLBCK
PLLACK
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