SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 430

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.3
Figure 26-1. General Clock Block Diagram
26.4
430
XOUT32/PA8
XOUT/PB8
XIN32/PA7
Block Diagram
Master Clock Controller
XIN/PB9
(Supply Controller)
SAM3S
XTALSEL
Clock Generator
RC Oscillator
4/8/12 MHz
Management
Embedded
32 kHz RC
Embedded
Resonator
Oscillator
32768 Hz
Oscillator
3-20 MHz
Oscillator
Status
Ceramic
Controller
Crystal
Crystal
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Fast
Power
or
Control
0
1
0
1
MOSCSEL
PLLB and
PLLA and
Divider /2
PLLBDIV2
PLLADIV2
Divider /2
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
Main Clock
MAINCK
Slow Clock
SLCK
SLCK
MAINCK
PLLBCK
PLLACK
Master Clock Controller
PLLACK
PLLBCK
(PMC_MCKR)
PLLBCK
MAINCK
PLLACK
SLCK
/1,/2,/3,/4,/8,
/16,/32,/64
Prescaler
PRES
USB Clock Controller (PMC_USB)
Programmable Clock Controller
(PMC_PCKx)
/1,/2,/4,/8,
/16,/32,/64
Prescaler
/1,/2,/3,...,/16
PRES
Divider
USBDIV
Peripherals
Clock Controller
(PMC_PCERx) ON/OFF
Sleep Mode
Processor
Controller
ON/OFF
Divider
Clock
/8
Free running clock
6500C–ATARM–8-Feb-11
Processor clock c
Master clock
USB Clock
HCLK
int
MCK
periph_clk[..
pck[..]
SysTick
FCLK
UDPCK