SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 435

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.12 Clock Failure Detector
6500C–ATARM–8-Feb-11
The clock failure detector allows to monitor the 3 to 20 MHz Crystal or Ceramic Resonator-
based oscillator and to detect an eventual defect of this oscillator (for example if the crystal is
unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the
clock failure detector is disabled too.
A failure is detected by means of a counter incrementing on the 3 to 20 MHzCrystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal
is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1
slow clock RC oscillator clock period. If, during the high level period of slow clock RC oscillator,
less than 8 fast crystal clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected,
the CFDEV flag is set in the PMC Status Register (PMC_SR), and can generate an interrupt if it
is not masked. The interrupt remains active until a read operation in the PMC_SR register. The
user can know the status of the clock failure detector at any time by reading the CFDS bit in the
PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source
clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or PLLBCK (CSS
= 2 or 3), then a clock failure detection switches automatically the Master Clock on MAINCK.
Then whatever the PMC configuration is, a clock failure detection switches automatically
MAINCK on the 4/8/12 MHz Fast RC Oscillator clock. If the Fast RC oscillator is disabled when a
clock failure detection occurs, it is automatically re-enabled by the clock failure detection
mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal or
Ceramic Resonator-based oscillator to the 4/8/12 MHz Fast RC Oscillator if the Master Clock
source is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACK
or PLLBACK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to
protect the driven device, if a clock failure is detected. This fault output remains active until the
defect is detected and until it is not cleared by the bit FOCLR in the PMC Fault Output Clear
Register (PMC_FOCR).
The user can know the status of the fault output at any time by reading the bit
PMC_SR register.
SAM3S
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