SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 488

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 28-4. Output Line Timings
28.5.8
28.5.9
488
488
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
SAM3S
SAM3S
Inputs
Input Glitch and Debouncing Filters
PIO_ODSR
PIO_PDSR
MCK
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter
Slow Clock Enable Register). Writing PIO_IFSCDR and PIO_IFSCER respectively, sets and
clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter
Slow Clock Status Register).
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2
Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on
PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a
duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse
durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
of Master Clock.
Period of the Programmable Divided Slow Clock.
APB Access
2 cycles
APB Access
2 cycles
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11