SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 530

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.7.49
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• PCEN: Parallel Capture Mode Enable
0 = The parallel capture mode is disabled.
1 = The parallel capture mode is enabled.
• DSIZE: Parallel Capture Mode Data Size
0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).
1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).
2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).
• ALWYS: Parallel Capture Mode Always Sampling
0 = The parallel capture mode samples the data when both data enables are active.
1 = The parallel capture mode samples the data whatever the data enables are.
• HALFS: Parallel Capture Mode Half Sampling
Independently from the ALWYS bit:
0 = The parallel capture mode samples all the data.
1 = The parallel capture mode samples the data only one time out of two.
• FRSTS: Parallel Capture Mode First Sample
This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from
0 to n:
0 = Only data with an even index are sampled.
1 = Only data with an odd index are sampled.
530
530
31
23
15
–
–
–
7
–
SAM3S
SAM3S
PIO Parallel Capture Mode Register
30
22
14
PIO_PCMR
0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC)
Read-write
–
–
–
6
–
29
21
13
–
–
–
5
DSIZE
28
20
12
–
–
–
4
“PIO Write Protect Mode Register”
FRSTS
27
19
11
–
–
–
3
HALFS
26
18
10
–
–
2
–
ALWYS
.
25
17
–
–
–
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
PCEN
24
16
–
–
8
–
0