SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 589

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 30-7.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
(from master)
(from slave)
TXEMPTY
NPCS0
SPCK
TDRE
MOSI
RDRF
MISO
SPI_TDR
Write in
Status Register Flags Behavior
Figure 30-7
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
Figure 30-8
of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags
behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the
Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data.
The next pointer and counter are not used. The RDRF and TDRE are not shown because these
flags are managed by the PDC when using the PDC.
MSB
1
MSB
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End
2
6
6
3
5
5
4
4
4
5
3
3
6
6
2
2
7
1
1
shift register empty
8
LSB
LSB
RDR read
SAM3S
SAM3S
589
589