SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 623

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 31-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 31-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
31.8.6.2
31.8.7
6500C–ATARM–8-Feb-11
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
Using the Peripheral DMA Controller (PDC)
S
S
S
10-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave
Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
Figure 31-13
the use of internal addresses to access the device.
Figure 31-13. Internal Address Usage
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
W
W
W
A
A
A
address)
IADR(23:16)
A
A
A
IADR(15:8)
IADR(7:0)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
IADR(23:16)
IADR(15:8)
IADR(7:0)
S
T
A
R
T
M
S
B
Address
Device
A
A
A
0
IADR(15:8)
Sr
IADR(7:0)
A
A
A
S
B
L
W
W
R
E
R
T
I
/
DADR
A
C
K
WORD ADDRESS
IADR(15:8)
IADR(7:0)
M
S
B
DATA
FIRST
A
A
R
Sr
IADR(7:0)
A
C
A
A
A
A
K
WORD ADDRESS
DADR
SECOND
IADR(7:0)
P
DATA
DATA
A
L
S
B
Sr
R
A
C
K
A
A
N
A
DADR
DATA
DATA
P
P
DATA
DATA
A
C
K
R
N
S
O
P
T
SAM3S
P
N
A
A
P
P
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