SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 74

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SAM3S1A

Manufacturer Part Number
SAM3S1A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1A

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.8.2.2
10.8.3
74
SAM3S
Power management programming hints
Wakeup from WFE
until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULT-
MASK see
The processor wakes up if:
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an
event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about the SCR see
page
ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the follow-
ing intrinsic functions for these instructions:
• it detects an exception with sufficient priority to cause exception entry
void __WFE(void) // Wait for Event
void __WFE(void) // Wait for Interrupt
173.
“Exception mask registers” on page
48.
“System Control Register” on
6500C–ATARM–8-Feb-11

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