SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 843

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36. Pulse Width Modulation Controller (PWM)
36.1
36.2
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The PWM macrocell controls 4 channels independently. Each channel controls two complemen-
tary square output waveforms. Characteristics of the output waveforms such as period, duty-
cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured
through the user interface. Each channel selects and uses one of the clocks provided by the
clock generator. The clock generator provides several clocks resulting from the division of the
PWM master clock (MCK).
All PWM macrocell accesses are made through registers mapped on the peripheral bus. All
channels integrate a double buffering system in order to prevent an unexpected output wave-
form while modifying the period, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle
or dead-times at the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA
Controller Channel (PDC) which offers buffer transfer without processor Intervention.
The PWM macrocell provides 8 independent comparison units capable of comparing a pro-
grammed value to the counter of the synchronous channels (counter of channel 0). These
comparisons are intended to generate software interrupts, to trigger pulses on the 2 indepen-
dent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of
the PWM outputs), and to trigger PDC transfer requests.
The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM block provides a fault protection mechanism with 6 fault inputs
fault condition and to override the PWM outputs asynchronously.
For safety usage, some control registers are write-protected.
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
• Independent channel programming
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
– Independent Enable Disable Commands
channel
, cap
able of detecting a
SAM3S
843