SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 874

• Manufacturer Part Number: SAM3S1A
• Manufacturer: Atmel Corporation

Specifications of SAM3S1A

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.5.5
874
SAM3S
Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the
channel 0 is enabled (see
To prevent unexpected comparison match, the user must use the
Update Register”
and PWM_CMPxMUPD) to change respectively the comparison values and the comparison
configurations while the channel 0 is still enabled. These registers hold the new values until the
end of the comparison update period (when CUPRCNT is equal to CUPR in
x Mode Register”
ues for the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be fol-
lowed by a write of the register PWM_CMPxMUPD.
Note:
Figure 36-19. Synchronized Update of Comparison Values and Configurations
If the update registers PWM_CMPxVUPD and PWM_CMPxMUPD are written several times
between two updates, only the last written value are taken into account.
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPxM written
End of channel0 PWM period and
end of Comparison Update Period
(PWM_CMPxM)) and the end of the current PWM period, then update the val-
and the
Section 36.6.3 “PWM Comparison
“PWM Comparison x Mode Update Register”
PWM_CMPxVUPD Value
Comparison Value
for comparison x
PWM_CMPxV
User's Writing
Units”).
PWM_CMPxMUPD Value
Comparison configuration
“PWM Comparison x Value
for comparison x
User's Writing
PWM_CMPxM
(PWM_CMPxVUPD
“PWM Comparison
6500C–ATARM–8-Feb-11