SAM3S1A Atmel Corporation, SAM3S1A Datasheet - Page 913

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SAM3S1A

Manufacturer Part Number
SAM3S1A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1A

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.7.33
Name:
Addresses:
Access:
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CV
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note:
CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be followed by a write of the register
PWM_CMPxMUPD.
6500C–ATARM–8-Feb-11
31
23
15
7
This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in
PWM Comparison x Value Update Register
30
22
14
PWM_CMPxVUPD
0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5],
0x40020194 [6], 0x400201A4 [7]
6
Write-only
29
21
13
5
28
20
12
4
UPD
CVUPD
CVUPD
CVUPD
are significant.
27
19
11
3
“PWM Channel Mode Register” on page
26
18
10
2
25
17
9
1
SAM3S
CVMUPD
24
16
916)
8
0
913

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