SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 115

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.13.6.4
10.13.6.5
6500C–ATARM–8-Feb-11
MOVS
MOV
MOVS
MOV
MOV
MVNS
Condition flags
Example
R11, #0x000B
R1, #0xFA05
R10, R12
R3, #23
R8, SP
R2, #0xF
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of
a BX or BLX instruction to branch for software portability to the ARM instruction set.
If S is specified, these instructions:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see
• do not affect the V flag.
page 80
; Write value of 0x000B to R11, flags get updated
; Write value of 0xFA05 to R1, flags are not updated
; Write value in R12 to R10, flags get updated
; Write value of 23 to R3
; Write value of stack pointer to R8
; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
“Flexible second operand” on
SAM3S
115