SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 121

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.14.2
10.14.2.1
10.14.2.2
10.14.2.3
10.14.2.4
10.14.2.5
6500C–ATARM–8-Feb-11
UMULL
SMLAL
UMULL, UMLAL, SMULL, and SMLAL
Syntax
Operation
Restrictions
Condition flags
Examples
R0, R4, R5, R6
R4, R5, R3, R8
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro-
ducing a 64-bit result.
where:
op
cond
RdHi, RdLo
Rn, Rm
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most signifi-
cant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies
these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo,
and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed inte-
gers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
In these instructions:
These instructions do not affect the condition code flags.
• do not use SP and do not use PC
• RdHi and RdLo must be different registers.
op{cond} RdLo, RdHi, Rn, Rm
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
is one of:
is an optional condition code, see
are the destination registers.
For UMLAL and SMLAL they also hold the accumulating value.
are registers holding the operands.
; Unsigned (R4,R0) = R5 x R6
; Signed (R5,R4) = (R5,R4) + R3 x R8
“Conditional execution” on page
84.
SAM3S
121