SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 134

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.17.3.4
10.17.3.5
134
ITTE
ANDNE
ADDSNE R2, R2, #1
MOVEQ
CMP
ITE
ADDGT
ADDLE
IT
ADDGT
ITTEE
MOVEQ
ADDEQ
ANDNE
BNE.W
IT
ADD
SAM3S
Condition flags
Example
NE
R0, R0, R1
R2, R3
R0, #9
GT
R1, R0, #55
R1, R0, #48
GT
R1, R1, #1
EQ
R0, R1
R2, R2, #10
R3, R3, #1
dloop
NE
R0, R0, R1
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the
use of assembler directives within them.
This instruction does not change the flags.
• a branch or any instruction that modifies the PC must either be outside an IT block or must be
• do not branch to any instruction inside an IT block, except when returning from an exception
• all conditional instructions except Bcond must be inside an IT block. Bcond can be either
• each instruction inside the IT block must specify a condition code suffix that is either the
the last instruction inside the IT block. These are:
handler
outside or inside an IT block but has a larger branch range if it is inside one
same or logical inverse as for the other instructions in the block.
– ADD PC, PC, Rm
– MOV PC, Rm
– B, BL, BX, BLX
– any LDM, LDR, or POP instruction that writes to the PC
– TBB and TBH
; Next 3 instructions are conditional
; ANDNE does not update condition flags
; ADDSNE updates condition flags
; Conditional move
; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
; Next 2 instructions are conditional
; Convert 0xA -> 'A'
; Convert 0x0 -> '0'
; IT block with only one conditional instruction
; Increment R1 conditionally
; Next 4 instructions are conditional
; Conditional move
; Conditional add
; Conditional AND
; Branch instruction can only be used in the last
; instruction of an IT block
; Next instruction is conditional
; Syntax error: no condition code used in IT block
6500C–ATARM–8-Feb-11