SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 284

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.5.6
Name:
Address:
Access:
• SMEN: Supply Monitor Wake Up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect.
1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect.
1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• WKUPDBC: Wake Up Inputs Debouncer Period
284
31
23
15
–
–
–
7
–
Value
0
1
2
3
4
5
6
7
SAM3S
Supply Controller Wake Up Mode Register
30
22
14
0x400E141C
–
–
6
–
SUPC_WUMR
Read-write
32768_SCLK
IMMEDIATE
4096_SCLK
512_SCLK
32_SCLK
Reserved
Reserved
3_SCLK
Name
WKUPDBC
29
21
13
–
–
5
–
Description
Immediate, no debouncing, detected active at least on one Slow Clock edge.
WKUPx shall be in its active state for at least 3 SLCK periods
WKUPx shall be in its active state for at least 32 SLCK periods
WKUPx shall be in its active state for at least 512 SLCK periods
WKUPx shall be in its active state for at least 4,096 SLCK periods
WKUPx shall be in its active state for at least 32,768 SLCK periods
Reserved
Reserved
28
20
12
–
–
4
–
RTCEN
27
19
11
–
–
–
3
RTTEN
26
18
10
–
–
–
2
SMEN
25
17
–
–
9
–
1
6500C–ATARM–8-Feb-11
24
16
–
–
8
–
0
–