SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 322

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.6
Table 20-1.
Note:
322
Offset
CRCCU_DSCR + 0x0
CRCCU_DSCR + 0x4
CRCCU_DSCR + 0xC - 0x10
CRCCU_DSCR + 0x10
Transfer Control Registers Memory Mapping
These Registers are memory mapped
SAM3S
Transfer Control Register Memory Mapping
To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode
Register (CRCCU_MR), then configure it and finally set the DMA enable bit (DMAEN) in the
CRCCU DMA Enable Register (CRCCU_DMA_EN).
When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in
TR_CTRL) located at TR_ADDR start address and computes the checksum.
The CRCCU_SR register contains the temporary CRC value.
The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decre-
mented if its value is different from zero. Once the value of the BTSIZE field is equal to zero, the
CRCCU is disabled by hardware. In this case, the relevant CRCCU DMA Status Register bit,
DMASR, is automatically cleared.
If the COMPARE field of the CRCCU_MR register is set to true, the TR_CRC (Transfer Refer-
ence Register) is compared with the last CRC computed. If a mismatch occurs, an error flag is
set and an interrupt is raised (if unmasked).
The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the
bandwidth usage of the system, but the DIVIDER field of the CRCCU Mode Register can be
used to lower it by dividing the frequency of the single accesses.
In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous
memory area, it is possible to re-enable the CRCCU on the new memory area and the CRC will
be updated accordingly. Use the RESET field of the CRCCU_CR register to reset the CRCCU
Status Register to its default value (0xFFFF_FFFF).
Register
CRCCU Transfer Address Register
CRCCU Transfer Control Register
Reserved
CRCCU Transfer Reference Register
TR_ADDR
TR_CTRL
TR_CRC
Name
6500C–ATARM–8-Feb-11
Read-write
Read-write
Read-write
Access