SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 365

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 23-4. Standard and “CE don’t care” NAND Flash Application Examples
6500C–ATARM–8-Feb-11
SMC
PIO
PIO
D[7:0]
A[22:21]
NANDOE
NANDWE
NCSx
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21of the address bus. Any bit of the address bus can also be
used for this purpose. The command, address or data words on the data bus of the NAND Flash
d e v i c e u s e th e i r o w n a d dr e s s e s w i th i n t h e N C S x a d d r es s s p a c e (c o n fi gu r e d b y
CCFG_SMCNFCS Register on the Bus Matrix User Interface). The chip enable (CE) signal of
the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then
remains asserted even when NCS3 is not selected, preventing the device from returning to
standby mode. The NANDCS output signal should be used in accordance with the external
NAND Flash device type.
Two types of CE behavior exist depending on the NAND flash device:
Figure 23-4
Not Connected
• PIO Input with pull-up enabled (default state after reset)
• PIO Output set at level 1
• Standard NAND Flash devices require that the CE pin remains asserted Low continuously
• This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal
during the read busy period to prevent the device from returning to standby mode. Since the
SAM3S Static Memory Controller (SMC) asserts the NCSx signal High, it is necessary to
connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low during the
busy period preceding data read out.
can be directly connected to the CE pin of the NAND Flash device.
illustrates both topologies: Standard and “CE don’t care” NAND Flash.
CE
R/B
ALE
CLE
NOE
NWE
AD[7:0]
NAND Flash
SMC
PIO
D[7:0]
A[22:21]
NANDOE
NANDWE
NCSx
CE
“CE don’t care”
NAND Flash
R/B
ALE
CLE
NOE
NWE
AD[7:0]
SAM3S
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