SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 485

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.5.1
28.5.2
28.5.3
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Pull-up and Pull-down Resistor Control
I/O Line or Peripheral Function Selection
Peripheral A or B or C or D Selection
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resis-
tor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up
Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in
setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in
PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The
pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down
Enable Register) and PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers
results in setting or clearing the corresponding bit in PIO_PPDSR (Pull-down Status Register).
Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0 means the pull-down
is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this
case, the write of PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the
pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write
of PIO_PUER for the concerned I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the
pull-downs are disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis-
ter PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates
whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of
0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A value of 1 indicates the pin is
controlled by the PIO controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),
PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR
resets at 1. However, in some events, it is important that PIO lines are controlled by the periph-
eral (as in the case of memory chip select lines that must be driven inactive after reset or for
address lines that must be driven low for booting out of an external memory). Thus, the reset
value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The
selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
For each pin:
• the corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in
• the corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in
• the corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in
PIO_ABCDSR2 means peripheral A is selected.
PIO_ABCDSR2 means peripheral B is selected.
PIO_ABCDSR2 means peripheral C is selected.
SAM3S
SAM3S
485
485