SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 550

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.7.8
29.7.9
550
550
SAM3S
SAM3S
Loop Mode
Interrupt
Note:
Figure 29-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is
connected to TF and RK is connected to TK.
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Reg-
ister) These registers enable and disable, respectively, the corresponding interrupt by setting
and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the
generation of interrupts by asserting the SSC interrupt line connected to the NVIC.
Figure 29-16. Interrupt Block Diagram
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on
1. STTDLY is set to 0.
the transmission. SyncData cannot be output in continuous mode.
TXBUFE
ENDTX
RXBUFF
ENDRX
PDC
RD
Transmitter
Receiver
Start = Enable Receiver
TXEMPTY
RXSYNC
TXSYNC
OVRUN
To SSC_RHR
RXRDY
TXRDY
DATLEN
Data
SSC_IER
To SSC_RHR
Set
DATLEN
SSC_IMR
Data
Interrupt
Control
SSC_IDR
Clear
SSC Interrupt
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11