SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 598

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
30.7.5
598
598
SAM3S
SAM3S
Write Protected Registers
To prevent any single software error that may corrupt SPI behavior, the registers listed below
can be write-protected by setting the SPIWPEN bit in the SPI Write Protection Mode Register
(SPI_WPMR).
If a write access in a write-protected register is detected, then the SPIWPVS flag in the SPI
Write Protection Status Register (SPI_WPSR) is set and the field SPIWPVSRC indicates in
which register the write access has been attempted.
The SPIWPVS flag is automatically reset after reading the SPI Write Protection Status Register
(SPI_WPSR).
List of the write-protected registers:
Section 30.8.2 ”SPI Mode Register”
Section 30.8.9 ”SPI Chip Select Register”
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11

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