SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 614

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.8.11
Name:
Address:
Access:
• SPIWPVS: SPI Write Protection Violation Status
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
614
614
31
23
15
–
–
7
–
SPIWPVS value
SAM3S
SAM3S
SPI Write Protection Status Register
0x1
0x2
0x3
0x4
0x5
0x6
0x7
30
22
14
SPI_WPSR
0x400080E8
Read-only
–
–
6
–
The Write Protection has blocked a Write access to a protected register (since the last read).
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx).
Both Write Protection violation and software reset with Write Protection enabled have occurred
since the last read.
Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
The Write Protection has blocked a Write access to a protected register and write accesses have
been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select
“i” was active) since the last read.
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx) and some write
accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while
the Chip Select “i” was active) since the last read.
- The Write Protection has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protection was enabled.
and
- Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
29
21
13
–
–
5
–
28
20
12
–
–
4
–
SPIWPVSRC
27
19
11
–
–
3
–
Violation Type
26
18
10
–
–
2
SPIWPVS
25
17
–
–
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
24
16
–
–
8
0