SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 636

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 31-25. Read Access Ordered by a MASTER
Notes:
31.10.5.2
Figure 31-26. Write Access Ordered by a Master
Notes:
636
EOSVACC
EOSVACC
SVREAD
SVREAD
SVACC
RXRDY
TXRDY
SVACC
NACK
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
TWD
TWD
SAM3S
acknowledged or non acknowledged.
Write Operation
S
S
ADR
ADR
TWI answers with a NACK
TWI answers with a NACK
SADR does not match,
SADR does not match,
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 31-26 on page 636
W
R
NA
NA
DATA
DATA
NA
NA
P/S/Sr
P/S/Sr
describes the Write operation.
Write THR
SADR
SADR
TWI answers with an ACK
TWI answers with an ACK
SADR matches,
SADR matches,
W A
R
SVREAD has to be taken into account only while SVACC is active
SVREAD has to be taken into account only while SVACC is active
A
DATA
DATA
A
A
Read RHR
ACK/NACK from the Master
A
A
DATA NA S/Sr
DATA
NA
6500C–ATARM–8-Feb-11
S/Sr
Read RHR

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