SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 86

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.11.7.3
The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1).
10.11.7.4
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater
than R1 and R2 is greater than R3.
10.11.8
10.11.8.1
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The exam-
ple below shows instructions with the instruction width suffix.
86
MOVS
IT
RSBMI
CMP
ITT
CMPGT
MOVGT
BCS.W
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
SAM3S
Instruction width selection
Absolute value
Compare and update value
Instruction width selection
label
R0, R1
MI
R0, R1, #0
R0, R1
GT
R2, R3
R4, R5
Table 10-16. Condition code suffixes (Continued)
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding
depending on the operands and destination register specified. For some of these instructions,
you can force a specific instruction size by using an instruction width suffix. The .W suffix forces
a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction
encoding of the requested width, it generates an error.
In some cases it might be necessary to specify the .W suffix, for example if the operand is the
label of an instruction or literal data, as in the case of branch instructions. This is because the
assembler might not automatically generate the right size encoding.
Suffix
VC
HI
LS
GE
LT
GT
LE
AL
; creates a 32-bit instruction even for a short branch
; operation can be done by a 16-bit instruction
; Compare R0 and R1, setting flags
; IT instruction for the two GT conditions
; If 'greater than', compare R2 and R3, setting flags
; If still 'greater than', do R4 = R5
Flags
V = 0
C = 1 and Z = 0
C = 0 or Z = 1
N = V
N != V
Z = 0 and N = V
Z = 1 and N != V
Can have any
value
; R0 = R1, setting flags
; IT instruction for the negative condition
; If negative, R0 = -R1
Meaning
No overflow
Higher, unsigned >
Lower or same, unsigned ≤
Greater than or equal, signed ≥
Less than, signed <
Greater than, signed >
Less than or equal, signed ≤
Always. This is the default when no suffix is
specified.
6500C–ATARM–8-Feb-11

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