SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 860

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Table 36-6.
860
Period Value
(
Dead-Time Values
(
Duty-Cycle Values
(
Update Period Value
(
PWM_CPRDUPDx)
PWM_DTUPDx)
PWM_CDTYUPDx)
PWM_SCUPUPD)
SAM3S
Summary of the Update of Registers of Synchronous Channels
PWM period as soon as the bit
Update is triggered at the next
• Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of
Update Period Register”
and automatic trigger of the update” on page
ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see
3: Automatic write of duty-cycle values and automatic trigger of the update” on page
The user can choose to synchronize the PDC transfer request with a comparison match (see
Section 36.6.3 “PWM Comparison
register.
UPDULOCK is set to 1
Write by the CPU
Not applicable
Not applicable
UPDM=0
(PWM_SCUP) (see
the bit UPDULOCK is set to 1
the bit UPDULOCK is set to 1
next PWM period as soon as
next PWM period as soon as
Update is triggered at the
Update is triggered at the
Units”), by the fields PTRM and PTRCS in the PWM_SCM
Write by the CPU
Write by the CPU
Write by the CPU
UPDM=1
PWM period as soon as the update period
PWM period as soon as the update period
counter has reached the value UPR
counter has reached the value UPR
862).
“Method 2: Manual write of duty-cycle values
Update is triggered at the next
Update is triggered at the next
Write by the CPU
Write by the PDC
UPDM=2
6500C–ATARM–8-Feb-11
“Method
864).

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