SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 932

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SAM3S1B

Manufacturer Part Number
SAM3S1B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S1B

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 37-5. Setup Transaction Followed by a Data OUT Transaction
37.6.2.2
932
Using Endpoints Without Ping-pong Attributes
USB
Bus Packets
RXSETUP Flag
RX_Data_BKO
(UDP_CSRx)
FIFO (DPR)
Content
SAM3S
Data IN Transaction
Setup
PID
Setup Received
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct
the transfer of data from the device to the host. Data IN transactions in isochronous transfer
must be done using endpoints with ping-pong attributes.
To perform a Data IN transaction using a non ping-pong endpoint:
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN
packet. An interrupt is pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note:
XX
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in
4. The application is notified that the endpoint’s FIFO has been released by the USB
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO,
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPK-
7. The application clears the TXCOMP in the endpoint’s UDP_CSRx.
Data Setup
endpoint’s UDP_CSRx register (TXPKTRDY must be cleared).
zero or more byte values in the endpoint’s UDP_FDRx register,
the endpoint’s UDP_CSRx register.
device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an
interrupt for the corresponding endpoint is pending while TXCOMP is set.
writing zero or more byte values in the endpoint’s UDP_FDRx register,
TRDY in the endpoint’s UDP_CSRx register.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the
Data IN protocol layer.
Set by USB Device
ACK
PID
Setup Handled by Firmware
Data OUT
PID
Interrupt Pending
Data Setup
Data OUT
Cleared by Firmware
NAK
PID
Data OUT
PID
Data Out Received
Set by USB
Device Peripheral
XX
Data OUT
6500C–ATARM–8-Feb-11
ACK
PID
Data
OUT

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