SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 987

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Oth-
erwise the parameters of CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as
shown in
Table 39-6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Chan-
nel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode.
Table 39-7.
OFFSET Bit
GAIN<0:1>
Table
00
01
10
11
0
1
Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G)
39-6.
OFFSET (DIFF = 0)
GAIN (DIFF = 0)
(G-1)Vrefin/2
1
1
2
4
0
OFFSET (DIFF = 1)
GAIN (DIFF = 1)
0.5
1
2
2
0
SAM3S
SAM3S
987
987