SAM3S1B Atmel Corporation, SAM3S1B Datasheet - Page 997

• Manufacturer Part Number: SAM3S1B
• Manufacturer: Atmel Corporation

Specifications of SAM3S1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.7.4
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 3. So it is only possible to use the sequencer from CH0 to CH3.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number
of consecutive values, this part of the conversion sequence being triggered by a unique event.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
31
23
15
–
–
–
7
–
ADC Channel Sequence 2 Register
30
22
14
ADC_SEQR2
0x4003800C
Read-write
6
USCH16
USCH14
USCH12
USCH10
29
21
13
5
28
20
12
4
“ADC Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
2
USCH15
USCH13
USCH11
USCH9
25
17
9
1
1013.
SAM3S
SAM3S
24
16
8
0
997
997