SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 1019

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.6.6
40.6.7
Figure 40-2. Conversion Sequence
6500C–ATARM–8-Feb-11
Write DACC_CDR
Selected Channel
Write USER_SEL
Read DACC_ISR
DAC Channel 0
DAC Channel 1
Output
Output
field
TXRDY
MCK
EOC
Sleep Mode
DACC Timings
None
Select Channel 0
The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when it is not
being used for conversions.
When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a
start-up time, the logic waits during this time and starts the conversion on the selected channel. When all
conversion requests are complete, the DACC is deactivated until the next request for conversion.
A fast wake-up mode is available in the
strategy and responsiveness. Setting the FASTW bit to 1 enables the fast wake-up mode. In fast wake-up
mode the DACC is not fully deactivated while no conversion is requested, thereby providing less power sav-
ing but faster wake-up (4 times faster).
The DACC startup time must be defined by the user in the STARTUP field of the
This startup time differs depending of the use of the fast wake-up mode along with sleep mode, in this case
the user must set the STARTUP time corresponding to the fast wake up and not the standard startup time.
A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using this mode, the
DAC Controller no longer waits to sample the end of cycle signal coming from the DACC block to start the
next conversion and uses an internal counter instead. This mode gains 2 DACC Clock periods between
each consecutive conversion.
Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it is 2 DACC
Clock periods late.
After 20 µs the analog voltage resulting from the converted data will start decreasing, therefore it is neces-
sary to refresh the channel on a regular basis to prevent this voltage loss. This is the purpose of the
REFRESH field in the DACC Mode Register where the user will define the period for the analog channels to
be refreshed.
Warning: A REFRESH PERIOD field set to 0 will disable the refresh function of the DACC channels.
Data 0 Data 1
Channel 0
Data 0
DACC Mode Register
Select Channel 1
Data 2
as a compromise between power saving
CDR FIFO not full
Data 1
Channel 1
DACC Mode
SAM3S
Data 2
Register.
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