SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 1102

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
1102
Doc. Rev.
6500B
SAM3S
Comments
Overview:
“Packages” on page
Table 1-1, “Configuration
Table 4-2, “100-ball LFBGA SAM3S4/2/1C
Figure 5-1, "Single
Figure 5-2, "Core Externally
2.0V-3.6V.
Section 7.2.3.8 “Unique
ACC:
Section 38.2 “Embedded
Table 38-1, “Analog Comparator Controller Block
hidden parts at top of block diagram revealed.
Section 38.7.2 “ACC Mode
ADC:
Section 39.7 “Analog-to-Digital Converter (ADC) User
LOWRES, SLEEP, FWUP, FREERUN, ANACH, USEQ. TSMODE, TSAV, TRGMOD)
CHIPID:
Section 27.2.1 “Chip ID
“EPROC: Embedded
“SRAMSIZ: Internal SRAM
Table 1-1, “ATSAM3S Chip IDs
CKGR/PMC:
Section 25.5.1 “4/8/12 MHz Fast RC
Section 25.5.2 “4/8/12 MHz Fast RC Oscillator Clock Frequency
Section 25.6.1 “Divider and Phase Lock Loop
oscillator at end of section.
Section 26.12 “Clock Failure
2 slow clock...”)
GPBR:
Section 17.2 “Embedded
HSMCI:
Section 35.2 “Embedded
Section 35.11 “HSMCI Boot Operation
Table 35-8, “Register
Section 35.14 “High Speed MultiMedia Card Interface (HSMCI) User
updated.
Table 35-8, “Register Mapping”
error corrected.
PIO:
Figure 28-3, "I/O Line Control
Input Filter Slow Clock Disable
28.7.28 “PIO Input Filter Slow Clock Status
Table 28-3, “Register
RTT:
“RTTRST: Real-time Timer
Supply",
1, package size or pitch updated.
Processor”,
Mapping”, Reserved offsets updated.
Mapping”, Reserved addresses updated below Schmitt Trigger line.
Register”, bitfields updated.
Identifier”, Each device integrates its own 128-bit unique identifier.
Characteristics”, references to “window function” removed.
Features”, there are eight general purpose backup registers on SAM3S devices.
Characteristics”, updated; Compatibility with SDIO Specification V2.0.
Summary”, ADC column updated, footnote gives precision on reserved channel.
Size”, replaced.
Register”, SELMINUS bitfield description relocated in front of SELPLUS
Restart”, in RTT_MR, bitfield updated; “0 = no effect”.
Figure 5-2, "Core Externally
Supplied",
Detector”, added 3rd paragraph (“A failure is detected...”) & 6th paragraph (“It takes
Logic",
Register”,
and
Register”, updated.
“ARCH: Architecture
Section 35.14.19 “HSMCI FIFOx Memory
Oscillator”, two paragraphs removed.
Section 28.5.9 “Input Glitch and Debouncing
Mode”, added “...not possible to boot directly on SD-CARD...”
Figure 5-3, "Backup
Section 28.7.27 “PIO Input Filter Slow Clock Enable
Pinout”, pinout information is available.
Register”; acronyms for ‘IFSxxx’ registers changed.
Programming”, added restraints on changing 4/8/12 MHz Fast RC
Diagram”, signal names beginning as “AD” updated and
Interface”, bitfield descriptions updated. (TRGEN,
Identifier”, updated.
Supplied", updated notes below figures.
Battery", ADC,DAC, Analog Comparator supply is
Adjustment”, added to datasheet
Interface”, bitfield description s and tables
Aperture”, HSMCI_FIFOx offset
Filters”,
Section 28.7.26 “PIO
Register”,
6500C–ATARM–8-Feb-11
Section
Change
Request
Ref.
7214
6981
7201
7243/rfo
7307
7103
6968
6865
6796
6796
6967/7166
7215
7129
7130
7127
7029
7091
6745
rfo:
7253
6875
7258
7143

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