SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 1104

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
1104
Doc. Rev.
6500B
SAM3S
Comments
Electrical Characteristics:
Table 41-2, “DC Characteristics”
Table 41-17, “4/8/12 MHz RC Oscillators
Table 41-7, “DC Flash
Table 41-21, “3 to 20 MHz Crystal Oscillator
Section 41.11 “AC
Table 41-45, “SPI
Table 41-46, “SSC
Table 41-47, “SMC Read Signals - NRD Controlled (READ_MODE =
Table 41-48, “SMC Read Signals - NCS Controlled (READ_MODE=
Table 41-49, “SMC Write Signals - NWE Controlled (WRITE_MODE =
Table 41-50, “SMC Write NCS Controlled (WRITE_MODE =
Table 41-51, “USART SPI
Table 41-53, “Embedded Flash Wait State VDDCORE set at
Table 41-54, “Embedded Flash Wait State VDDCORE set at 1.80V”
Section 41.11.3.1 “Maximum SPI
“Master Read Mode”
“Slave Write Mode”
Section 41.11.7 “USART in SPI Mode
Figure
Table 41-28, “Analog Power Supply
Table 41-29, “Channel Conversion Time and ADC
Table 41-30, “External Voltage Reference
Table 41-35, “Analog
Section 41.7.0.1 “Track and Hold Time versus Source Output
Figure
Table 41-51, “USART SPI
Errata:
Section 44. “SAM3S Series
41-28,
41-30, SPI
Figure
14
Timings”,
Characteristics”, updated the following tables
Timings”,
...2x(SPI
and SPI
41-28, updated with text on line drives.
...F
Inputs”, Input Capacitance, Max value updated.
Characteristics”, 1st cell , I
SPCK
Timings”,
Timings”, all references to SPCK changed to SCK. Min values updated.
15
Errata”, added to the datasheet.
6max
Max = 33 MHz...
repositioned in respect to SCK rising and falling.
(orSPI
V
Frequency”, the following changes:
OH
Characteristics”, updated I
/V
Timings”, all figures, tables and titles renamed USART from UART.
OL
9max
Characteristics”, updated.
Min/Max values swapped.
Input”, removed ADVREF Settling Time.
) ......F
Characteristics”, C
SB
SPCK
Clock”, f
deleted.
Max = 25 MHz...
ADC
0)”,
1.65V”,
, t
Impedance”, replaced text below figure.
VDDANA
LEXT
CP_ADC ,
line modified.
0)”,
1)”,
line.
1)”,
t
START-UP
lines updated & added t
6500C–ATARM–8-Feb-11
SETTLING
Change
Request
Ref.
7208
rfo
rfo
rfo
7225
rfo
rfo
7320
7207/7316

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