SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 179

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.21.10 System Handler Control and State Register
• USGFAULTENA
Usage fault enable bit, set to 1 to enable
• BUSFAULTENA
Bus fault enable bit, set to 1 to enable
• MEMFAULTENA
Memory management fault enable bit, set to 1 to enable
• SVCALLPENDED
SVC call pending bit, reads as 1 if exception is pending
• BUSFAULTPENDED
Bus fault exception pending bit, reads as 1 if exception is pending
• MEMFAULTPENDED
Memory management fault exception pending bit, reads as 1 if exception is pending
• USGFAULTPENDED
Usage fault exception pending bit, reads as 1 if exception is pending
• SYSTICKACT
SysTick exception active bit, reads as 1 if exception is active
• PENDSVACT
PendSV exception active bit, reads as 1 if exception is active
1.
2.
3.
6500C–ATARM–8-Feb-11
SVCALLPENDE
SVCALLAVCT
31
23
15
D
7
Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of
status of the exceptions.
the exceptions, but see the Caution in this section.
BUSFAULTPEND
ED
30
22
14
6
The SHCSR enables the system handlers, and indicates:
See the register summary in
ments are:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
MEMFAULTPEN
Reserved
Reserved
DED
29
21
13
5
(3)
(1)
USGFAULTPEND
28
20
12
ED
4
Table 10-30 on page 164
(2)
(3)
Reserved
(3)
USGFAULTACT
SYSTICKACT
(2)
27
19
11
3
(2)
USGFAULTENA
PENDSVACT
Reserved
for the SHCSR attributes. The bit assign-
26
18
10
2
(2)
BUSFAULTENA
BUSFAULTACT
Reserved
25
17
9
1
SAM3S
MEMFAULTENA
MEMFAULTACT
MONITORACT
24
16
8
0
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