SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 393

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
23.14 Asynchronous Page Mode
23.14.1
Figure 23-31. Page Mode Read Protocol (Address MSB and LSB are defined in
6500C–ATARM–8-Feb-11
Protocol and Timings in Page Mode
A[MSB]
A[LSB]
D[7:0]
MCK
NRD
NCS
The SMC supports asynchronous burst reads in page mode, providing that the page mode is
enabled in the SMC_MODE register (PMEN field). The page size must be configured in the
SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t
quent accesses to the page (t
enables the user to define different read timings for the first access within one page, and next
accesses within the page.
Table 23-5.
Note:
Figure 23-31
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
Page Size
4 bytes
8 bytes
16 bytes
32 bytes
1. “A” denotes the address bus of the memory device.
NCS_RD_PULSE
shows the NRD and NCS timings in page mode access.
Page Address and Data Address within a Page
tpa
Page Address
A[23:2]
A[23:3]
A[23:4]
A[23:5]
sa
) as shown in
(1)
NRD_PULSE
tsa
Table
Figure
23-5.
Table
23-31. When in page mode, the SMC
Data Address in the Page
A[1:0]
A[2:0]
A[3:0]
A[4:0]
NRD_PULSE
23-5)
pa
tsa
) takes longer than the subse-
SAM3S
393

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