SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 501

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 28-3.
Notes:
Note:
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Offset
0x150
0x154
0x158
0x15C
0x160
0x164
0x0168
to
0x018C
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
if an offset is not listed in the table it must be considered as reserved.
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
occurred.
Register
Parallel Capture Mode Register
Parallel Capture Interrupt Enable Register
Parallel Capture Interrupt Disable Register
Parallel Capture Interrupt Mask Register
Parallel Capture Interrupt Status Register
Parallel Capture Reception Holding Register
Reserved for PDC Registers
Register Mapping (Continued)
Name
PIO_PCMR
PIO_PCIER
PIO_PCIDR
PIO_PCIMR
PIO_PCISR
PIO_PCRHR
Read-write
Write-only
Write-only
Read-only
Read-only
Read-only
Access
SAM3S
SAM3S
0x00000000
0x00000000
0x00000000
0x00000000
Reset
–
–
501
501