SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 56

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.5.3
10.5.3.1
56
SAM3S
Behavior of memory accesses
Additional memory access constraints for shared memory
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
The behavior of accesses to each region in the memory map is:
Table 10-4.
1.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as
Table 10-5.
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
Address range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
See
“Memory regions, types and attributes” on page 54
Memory access behavior
Memory region share ability policies
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private
Peripheral
Bus
Reserved
“Memory protection unit” on page
Memory region
Code
SRAM
Peripheral
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XN
-
-
XN
-
XN
XN
XN
Memory type
Normal
Normal
Device
Table 10-5
Description
Executable region for program code. You can also put
data here.
Executable region for data. You can also put code
here.
This region includes bit band and bit band alias areas,
see
This region includes bit band and bit band alias areas,
see
Executable region for data.
External Device memory
This region includes the NVIC, System timer, and
system control block.
Reserved
Table 10-6 on page
Table 10-6 on page
196.
(1)
(1)
(1)
shows:
for more information.
Shareability
-
-
-
58.
58.
6500C–ATARM–8-Feb-11

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