SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 830

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a
free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command
(CMD12).
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data
block.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
• ENDTX: End of TX Buffer
0 = The Transmit Counter Register has not reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
Note:
• SDIOIRQA: SDIO Interrupt for Slot A
0 = No interrupt detected on SDIO Slot A.
1 = An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.
• SDIOWAIT: SDIO Read Wait Operation Status
0 = Normal Bus operation.
1 = The data bus has entered IO wait state.
• CSRCV: CE-ATA Completion Signal Received
0 = No completion signal received since last status read operation.
1 = The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR
register.
• RXBUFF: RX Buffer Full
0 = HSMCI_RCR or HSMCI_RNCR has a value other than 0.
1 = Both HSMCI_RCR and HSMCI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = HSMCI_TCR or HSMCI_TNCR has a value other than 0.
1 = Both HSMCI_TCR and HSMCI_TNCR have a value of 0.
Note:
830
BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only
transferred from the PDC to the HSMCI Controller.
BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only
transferred from the PDC to the HSMCI Controller.
SAM3S
6500C–ATARM–8-Feb-11